#ifndef _PLC_OPCODES_H_
#define _PLC_OPCODES_H_

#define VAL(l, m, n) ((l << 2 | m << 1 | n) << 1)

//	*BYTE
//	*BYTE*BIT

enum Opcodes{
	LOAD =				0x10,
		//	*0(ld, *7 - li)
		//	*1(F, F) dest/org register
		//	*3*0 = update

	STORE =				0x10 | VAL(0,0,1),
		//	*0(std, *7 - sti)
		//	*1(F, F) org/dest register
		//	*3*0 = update
	
	BRANCH =			0x20,

	BRANCH_LINK =		0x20 | VAL(0,0,1),

	BRANCH_INDIRECT =	0x20 | VAL(0,1,0),

	BRANCH_EQUAL	=	0x30,

	BRANCH_LESS		=	0x30 | VAL(0,0,1),

	BRANCH_LESS_EQ	=	0x30 | VAL(0,1,0),

	ROTL			=	0x40,
	ROTR			=	0x40 | VAL(0,0,1),

	NOT				=	0x40 | VAL(0,1,0),
	AND				=	0x40 | VAL(0,1,1),


};

#endif